FIG. 1 shows the general schematic block diagram of the architecture of a conventional asynchronous BiCMOS SRAM circuit 1 with which the LATD circuit of the present invention may be used. The SRAM circuit basically includes a mxp CMOS memory cell array identified by numeral 2, X (or row) and Y (or column) address decoder circuits respectively referenced 3 and 4, and the data transfer and sense amplifier circuits in block 5. The X decoder circuit 3 or word line (WL) selection circuit selects one word line in response to the X address word (addresses X1 to Xk). The Y decoder circuit 4 or bit line (BL) selection circuit selects one sense amplifier corresponding to one pair of bit lines in response to the Y address word (addresses Y1 to Y.sub.--). Conventionally, memory cell array 2 is constructed by a plurality of individual memory cells generically referenced MC arranged in a matrix. Typically, each of memory cells is of the 6-device type and comprises a flip-flop formed by a pair of cross-coupled NFETs loaded by resistors or PFETs and a pair of transfer gates consisting of NFETs. All memory cells of a same column are connected between a pair of bit lines, while all the memory cells of a same row are connected to the same word line. X and Y address bits are stored in respective individual address buffers or receivers arranged in two blocks referenced 6-A and 6-B. Typically, address buffer blocks 6-A and 6-B are part of a general address buffer block 6 which receives all the address bits A1 to An including both X and Y address bits as shown in FIG. 1. The selected sense amplifier in block 5 amplifies the signal that appears between the corresponding pair of bit lines and generates a signal that is representative of the binary data stored in the selected cell to output buffer 7. The data out (DO) signal is available at the output terminal 8 thereof.
SRAM circuit 1 further includes a control logic circuitry typically comprising two local address transition detection (LATD) circuits in blocks 9-A and 9-B, respectively corresponding to the X and Y address buffer blocks 6-A and 6-B, a main address transition detection (MATD) circuit 10 and a control logic circuit 11. Similarly, LATD blocks 9-A and 9-B are part of a general LATD block 9 which therefore comprises n individual LATD circuits, one for each address buffer or address bit. References are therefore given with correspondence therebetween, e.g., address bit Ai (i=1 to n) corresponds to address buffer 6-i and LATD circuit 9-i, the latter generating a pulse signal LATDSi.
Each LATD circuit detects a transition of the corresponding address bit signal. When a transition occurs, in at least one address bit, e.g., in bit Ai, the corresponding LATD circuit, e.g., LATD 9-i, outputs a local address transition detection signal, e.g., LATDSi of a determined width. MATD circuit 10 is basically an OR gate, since it makes the summation of all LATDS signals supplied by the n LATD circuits, i.e., signals LATDSl to LATDSk originating from LATD block 9-A via bus 12-A and signals ATDSk+1 to ATDSn originating from LATD block 9-B via bus 12-B. MATD circuit 10 generates a signal referenced MATDS, that is applied to control circuit 11 via line 13. In turn, control circuit 11 controls operation of X decoder 3, Y decoder 4, and sense amplifier circuits in block 5, respectively, through control lines 14, 15 and 16. This technique is used to generate a pulsed word line signal that closes the transfer gates of the memory cells after a READ or a WRITE operation in order to avoid DC current consumption in the array when no cell is selected. Connection lines between address buffer block 6-A and X decoder 3 on the one hand, and between address buffer block 6-B and Y decoder 4 on the other hand, are respectively made through busses 17 and 18. Finally, the connection lines between Y decoder 4 and the sense amplifier block 5 are grouped in a bus referenced 19.
Typically, the SRAM circuit of FIG. 1 is constructed in the BiCMOS technology. CMOS device manufacturing methods have many processing steps that are compatible with bipolar device manufacturing methods. Recently, new methods have been developed to implement both CMOS and bipolar devices on the same chip to take benefit of their respective advantages, leading to the so-called BiCMOS technology. In particular, in SRAMs, the use of 6-device cells in CMOS technology presents many advantages in terms of integration density (which leads to highly integrated memory chips) and in improved manufacturing yields. On the other hand, in addition to their high switching speed, bipolar devices have a number of intrinsic advantages compared to CMOS devices when used in certain applications, such as in sense amplifiers. Bipolar devices are appreciated for their outstanding driving capabilities of capacitive loads due to their high current gain. Also, bipolar devices require smaller transitions on signal swings than CMOS devices. However, extensive usage of bipolar devices has been limited because of their large power dissipation. As a result, both bipolar devices (such as of the ECL type) and CMOS devices are simultaneously found in the same chip. A major concern is that the high and low voltage (or logic) levels in ECL circuits are different than those in CMOS circuits. For example, typical ECL circuits operate with standard high and low voltage levels of approximately -0.9 and -1.7 volts respectively, while typical CMOS circuits operate with high and low voltage levels of about -0.4 and -4.1 volts respectively. Therefore, in order to couple the output of an ECL circuit to the input of a CMOS circuit, a converting circuit is commonly employed to change the logic levels. For example, most of the BiCMOS stand-alone SRAM chips require converters with ECL compatible input voltage levels and CMOS compatible output voltage levels.
As illustrated by the conventional BiCMOS SRAM circuit of FIG. 1, basically the combination of a low power consumption, high density, CMOS memory cell array 2 with BiCMOS sense amplifiers and address decoders, provides an excellent compromise between density and speed in cost competitive SRAMs. Conventionally, in addition to the sense amplifiers and address decoders mentioned above, output buffer 7 and control logic circuit 11 are also BiCMOS circuits, while the circuits forming the LATD block 9, the address buffer block 6 and the MATD circuit 10 are pure CMOS circuits.
For example, with respect to the circuit of FIG. 1, a similar BiCMOS SRAM circuit architecture is illustrated in the article: "An 8-ns 1 Mbit ECL BiCMOS SRAM with double latch ECL to CMOS level converters" by M. Matsui et al published in IEEE JSSC (USA) vol. 24, N.degree.5, October 1989, p 1226-1232. As apparent from FIG. 1 of this article, once the address signals X0-X8, Y0-Y10 at the ECL voltage levels have been converted in CMOS voltage levels by the ECL to CMOS converter, the remaining circuits in the address buffer block and the LATD block comprise pure CMOS circuits. In that respect, a detailed description of a pure CMOS LATD circuit is described in the article "Two 13-ns 64 K CMOS SRAM's with very low active power and improved asynchronous circuit techniques", by S. T. Flannagan et al., IEEE JSSC, vol. SC-21, N.degree.5, Oct. 1986, pp 692-696
Because, there is a continuous attempt to improve performance in advanced high speed BiCMOS SRAM circuits, more attention has been given to LATD circuits. As these SRAM circuits reach the 10 ns access time range, the address transition detection role becomes more and more important. This function occurs in the critical delay path that allows a store or a sense (read) of the memory to occur once an address transition has been detected and is, therefore, determinative of the total access time.
Pure CMOS LATD circuits do not appear to have the potential to fulfill the high speed requirements that are now desired for the implementation of advanced high speed SRAM circuits for a number of reasons. First, CMOS circuits are intrinsically slow circuits because they require a delay corresponding to the time needed to make the transition of a threshold voltage (VT) to trigger a FET device. This point is illustrated by the LATD circuit described in the article by S. T. Flannagan et al. referenced above. As apparent from FIG. 3(a) of the Flannagan et al. article, the output signal generated by logic gate 3 drives an input circuit comprising a NFET and a PFET. The latter will enter in conduction only when said output signal becomes higher than its VT.
In addition, CMOS circuits tend to be slow because they generally deliver full swing output voltages, which take more time for delivery, as compared with bipolar circuits that supply small swing output voltages. This characteristic is also illustrated in FIG. 3(a) of the Flannagan et al. article, where logic gate 3 generates a full swing logic signal to the LATD circuit, which, in turn, also delivers a full swing output signal. Moreover, conventional SRAM circuits such as shown in the Matsui et al. article discussed above, require that the ECL to CMOS conversion be completely terminated before the address bit signal at the CMOS levels is applied to the corresponding LATD circuit. This again slows down the signal transmission to the address buffer.
Finally, many known implementations of LATD circuits include PFETs. For example, with respect to the LATD circuit illustrated in the Flannagan et al. article two PFETs are connected in series in each branch to achieve the pull-up effect. PFETs are known to be slow devices.